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| Integrating Mixed-Signal Solutions PRELIMINARY DATA SHEET STAC9460/62 Two and Six-Channel, 24-Bit, 192 kHz Audio Codec PRELIMINARY INFORMATION 8/24/01 2-9460-D1-1-0-0801 Copyright (c) 2001 SigmaTel, Inc. All rights reserved. All contents of this document are protected by copyright law and may not be reproduced without the express written consent of SigmaTel, Inc. I2C is a registered trademark of Philips Semiconductor and requires a license for use of the I2C bus interface. SigmaTel, the SigmaTel logo, and combinations thereof are trademarks of SigmaTel, Inc. Other product names used in this publication are for identification purposes only and may be trademarks or registered trademarks of their respective companies. The contents of this document are provided in connection with SigmaTel, Inc. products. SigmaTel, Inc. has made best efforts to ensure that the information contained herein is accurate and reliable. However, SigmaTel, Inc. makes no warranties, express or implied, as to the accuracy or completeness of the contents of this publication and is providing this publication "AS IS". SigmaTel, Inc. reserves the right to make changes to specifications and product descriptions at any time without notice, and to discontinue or make changes to its products at any time without notice. SigmaTel, Inc. does not assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential, or incidential damages. PRELIMINARY INFORMATION 8/24/01 STAC9460/62 Two and Six-Channel, 24-Bit, 192 kHz Audio Codec 1. TABLE OF CONTENTS 1. TABLE OF CONTENTS ............................................................................................................. 2 1.1. List of Figures ....................................................................................................................................3 1.2. List of Tables ......................................................................................................................................3 2. PRODUCT BRIEF ...................................................................................................................... 4 2.1. FEATURES ........................................................................................................................................4 2.2. Ordering Information ..........................................................................................................................5 2.3. Block Diagram ....................................................................................................................................5 2.4. Related Materials ...............................................................................................................................5 2.5. Additional Support ..............................................................................................................................5 3. CHARACTERISTICS AND SPECIFICATIONS ......................................................................... 6 3.1. Absolute Maximum Ratings ...............................................................................................................6 3.2. Recommended Operating Conditions ..............................................................................................6 3.3. Power Consumption .........................................................................................................................6 3.4. Static Digital Specifications ................................................................................................................6 3.5. STAC9460 Analog Performance Characteristics ...............................................................................7 4. TYPICAL CONNECTION DIAGRAM ......................................................................................... 8 5. SERIAL INTERFACE ................................................................................................................. 9 5.1. Clocking .............................................................................................................................................9 5.2. Reset ..................................................................................................................................................9 6. DIGITAL AUDIO INTERFACE ................................................................................................10 6.1. I2S Serial Interface ..........................................................................................................................10 6.2. Single Line Format ..........................................................................................................................11 6.3. I2C-Bus Interface .............................................................................................................................11 7. PROGRAMMABILITY ..............................................................................................................13 7.1. List of Registers ...............................................................................................................................14 7.1.1. Reset/Status Register (00h) ...............................................................................................14 7.1.2. Status Register (01h) .........................................................................................................14 7.1.3. Master Volume Register (02h) ...........................................................................................14 7.1.4. LF/RF, LR/RR, Center/LFE Output Channel Volume Registers(03h-08h) .........................15 7.1.5. Microphone Input Volume Registers (09h-0Ah) .................................................................15 7.1.6. De-Emphasis Register (0Ch) .............................................................................................15 7.1.7. General Purpose Register (0Dh) ........................................................................................16 7.1.8. Audio Port Control (0Eh) ....................................................................................................16 7.1.9. Master Clocking Register (0Fh) .........................................................................................17 7.1.10. Powerdown Control Registers (10h-11h) .........................................................................18 7.1.11. Revision Code Register (12h) ..........................................................................................18 7.1.12. Address Control Register/Address Register (13h-14h) ....................................................18 8. PIN DESCRIPTION ..................................................................................................................19 8.1. STAC9460 Pin and Signal Description ............................................................................................19 8.2. STAC9462 Pin and Signal Description ............................................................................................19 8.3. Digital I/O .........................................................................................................................................20 8.4. Analog I/O ........................................................................................................................................20 8.5. Filter/References ..............................................................................................................................20 8.6. Power and Ground Signals ..............................................................................................................21 9. PACKAGE DRAWING .............................................................................................................22 2 2-9460-D1-1-0-0801 PRELIMINARY INFORMATION 8/24/01 STAC9460/62 Two and Six-Channel, 24-Bit, 192 kHz Audio Codec 1.1. List of Figures Figure 1. STAC9460 Block Diagram ................................................................................................................5 Figure 2. Typical Connection Diagram .............................................................................................................8 Figure 3. Serial interface to microcontroller or microprocessor ........................................................................9 Figure 4. I2S Format .......................................................................................................................................10 Figure 5. I2S Left Justified Format .................................................................................................................10 Figure 6. I2S Right Justified Format ...............................................................................................................10 Figure 7. Single Line Data Mode Timing Diagram .........................................................................................11 Figure 8. I2C Timing Diagram .........................................................................................................................11 Figure 9. STAC9460 Pin Designation ...........................................................................................................19 Figure 10. STAC9462 Pin Designation ..........................................................................................................19 Figure 11. Package Outline ............................................................................................................................22 1.2. List of Tables Table 1. Digital Audio Interface Configuration ................................................................................................10 Table 2. Single Line Data Mode, Data Valid on Rising Edge of SCLK ...........................................................11 Table 3. I2C Mode Specifications ...................................................................................................................12 Table 4. Programming Registers ....................................................................................................................13 Table 5. Reset/Status Register ......................................................................................................................14 Table 6. Master Volume Register ...................................................................................................................14 Table 7. DAC Digital Volume Registers .........................................................................................................15 Table 8. Left and Right Mic Input Volume Registers ......................................................................................15 Table 9. On/Off De-emphasis Selection for Each Channel ............................................................................15 Table 10. De-emphasis Filter Selection .........................................................................................................15 Table 11. MSB Microphone/Differential Input Selection .................................................................................16 Table 12. Bit D6 ADC High Pass Filter Disable ..............................................................................................16 Table 13. Bit D5 Microphone DifferentialMux By-Pass Control ......................................................................16 Table 14. Audio Data Format Selection .........................................................................................................16 Table 15. Sample Rate Mode ........................................................................................................................17 Table 16. MCLK Mode ...................................................................................................................................17 Table 17. Powerdown Control ........................................................................................................................18 Table 18. Digital Signal List ............................................................................................................................20 Table 19. Analog Signal List ..........................................................................................................................20 Table 20. Filtering and Voltage References ...................................................................................................20 Table 21. Power Signal List ...........................................................................................................................21 2-9460-D1-1-0-0801 3 PRELIMINARY INFORMATION 8/24/01 STAC9460/62 Two and Six-Channel, 24-Bit, 192 kHz Audio Codec 2. PRODUCT BRIEF SigmaTel's STAC9460/62 are six and two-channel general-purpose 24-bit, full duplex, audio codecs for use in consumer applications. The STAC9460/62 incorporate SigmaTel's proprietary Sigma-Delta technology to achieve ADC and DAC SNRs in excess of 100 dB. The DACs, and ADCs are integrated with analog I/Os, which include two differential analog and two MIC inputs. There are three audio I2S inputs and an I2S digital output. The STAC9460/62 communicates via a standard two-wire serial interface providing simplicity in the audio system design. Packaged in a 28pin SSOP, the STAC9460 and STAC9462 require minimal PCB space for implementation. The STAC9460 provides variable sample rate D-A and A-D conversion, as well as analog processing. Supported DAC audio sample rates include 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz, 176.4 kHz and 192 kHz. Supported ADC audio sample rates inclued 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz,and 96 kHz. The digital data interface communicates via a standard I2C(R) compatible serial control interface and I2S digital audio interface. The stereo sample rate ADC's provide record capability from the microphone inputs or the differential inputs. All DAC's operate at 24-bit resolution with the sample rate based on the MCLK and programmable registers. The ADCs operate at 24-bit resolution and supply full 24-bit filter data. The STAC9460 supports three I2S digital audio inputs and an I2S digital audio output. These digital I/O options provide for a number of advanced architectural implementations, with volume controls and mute capabilities built directly into the codec for each individual channel. The output volume ranges from 0 dB to -95 dB with .75 dB steps. For MIC input, the input volume ranges from 0 dB to 22.5 dB with 1.5 dB steps. The STAC9460 also supports a single-line format. The STAC9460 is designed primarily to support 6-channel audio. True AC-3 playback can be achieved for 6-speaker applications by taking advantage of the STAC9460 architecture and combining it with the appropriate processing. This product is ideal for home theatre, DVD, karaoke, and set-top-box applications. 2.1. FEATURES * * * * * * * * * * * * * * High performance technology Two or six channels with independent volume controls 24-bit full duplex stereo DACs 24-bit full duplex stereo ADC 32, 44.1, 48, 88.2, 96, 176.4 and 192 kHz DAC sample rates 32, 44.1, 48, 88.2 and 96 kHz ADC sample rates Standard I2C compatible and I2S serial interfaces Digital de-emphasis capability DAC and ADC SNR >100 dB Differential Stereo Analog Input Dual mic inputs with independent volume controls 28-pin SSOP package Energy saving dynamic power modes 5V Analog with 3.3V or 5V Digital capability 4 2-9460-D1-1-0-0801 PRELIMINARY INFORMATION 8/24/01 STAC9460/62 Two and Six-Channel, 24-Bit, 192 kHz Audio Codec 2.2. Ordering Information PART NUMBER CHANNELS PACKAGE TEMPERATURE RANGE SUPPLY RANGE AVdd = 5V, DVdd = 3.3V or 5V STAC9460S 6 DAC; 2 ADC 28-pin SSOP 0 oC to +70 C STAC9462S 2 DAC; 2 ADC 28-pin SSOP 0 oC to +70 C AVdd = 5V, DVdd = 3.3V or 5V STEECBAC9460B (Evaluation Board): please send email request to apps@sigmatel.com Note: SigmaTel reserves the right to change specifications without notice. 2.3. Block Diagram CS SCLK SDATA RESET I2C(R) Port VOLUME VOLUME MUX DIFF_L DIFF_GND DIFF_R ADC DSP VOLUME SDI1 SDI2 SDI3 D_SCLK D_LRCLK SDATA_OUT DAC DAC_RR ADC VOLUME DAC DAC_RF MIC_L MIC_R VOLUME DAC DAC_LF VOLUME DAC DAC_LR I2S Port VOLUME DAC DAC_CTR VOLUME DAC DAC_BASS MCLK CAP DVdd DVss VREF AVdd AVss Figure 1. STAC9460 Block Diagram 2.4. Related Materials * * * Product Brief Evaluation Boards Reference Designs 2.5. Additional Support Additional product and company information can be obtained by going to the SigmaTel website at: www.sigmatel.com 2-9460-D1-1-0-0801 5 PRELIMINARY INFORMATION 8/24/01 STAC9460/62 Two and Six-Channel, 24-Bit, 192 kHz Audio Codec 3. CHARACTERISTICS AND SPECIFICATIONS 3.1. Absolute Maximum Ratings Voltage on any pin relative to Ground Operating Temperature Storage Temperature Soldering Temperature Output Current per Pin Vss - 0.3 V TO Vdd + 0.3 V 0 C TO 70 C -55 oC TO +125 C 260 C FOR 10 SECONDS 4 mA 3.2. Recommended Operating Conditions PARAMETER MIN + 3.3 V Digital + 5 V Digital + 5 V Analog 3.135 4.75 4.75 0 TYP 3.3 5 5 MAX 3.435 5.25 5.25 70 UNITS V V V C Power Supplies Ambient Temperature 3.3. Power Consumption PARAMETER MIN + 5 V Digital + 3.3 V Digital + 5 V Analog TYP 50 30 70 MAX UNITS mA mA mA Digital Supply Current Analog Supply Current 3.4. Static Digital Specifications (Tambient = 25 oC, DVdd = 5.0 V or 3.3 V 5%, AVss=DVss=0 V; 50pF external load) PARAMETER SYMBOL Vin Vil Vih Voh Vol MIN -0.30 0.65xDVdd 0.90xDVdd -10 -10 4 TYP MAX DVdd + 0.30 0.30xDVdd 0.2xDVdd 10 10 UNITS V V V V V uA uA mA Input Voltage Range Low level input range High level input voltage High level output voltage Low level output voltage Input Leakage Current (Digital inputs) Output Leakage Current (Digital outputs) Output buffer drive current 6 2-9460-D1-1-0-0801 PRELIMINARY INFORMATION 8/24/01 STAC9460/62 Two and Six-Channel, 24-Bit, 192 kHz Audio Codec 3.5. STAC9460 Analog Performance Characteristics (Tambient = 25 C, AVdd = 5.0V 5%, DVdd = 5.0V 5%, AVss=DVss=0V; 1 kHz input sine wave; Sample Frequency = 48 kHz; 0 dB = 1 Vrms, 10 K/50 pF load, Testbench Characterization BW: 20 Hz - 20 kHz, 0 dB settings on all gain stages) PARAMETER Full Scale Input Voltage: Differential Inputs Mic Inputs Full Scale Output Voltage: Line Output 5V Analog Frequency Response (Note 1) Digital S/N (Note 2) D/A 5V A/D 5V Total Harmonic Distortion: Line Output (Note 3) D/A Frequency Response (Note 4) A/D Frequency Response (Note 4) Transition Band(Note 6) Stop Band(Note 6) Deviation from Linear Phase (Note 6) Stop Band Rejection Out-of-Band Rejection (Note 7) Group Delay Power Supply Rejection Ratio (1kHz) Crosstalk between Input channels Spurious Tone Rejection Mic Gain Step Size Mic Input Impedance Differential Input Impedance Input Capacitance VREFout Interchannel Gain Mismatch ADC Interchannel Gain Mismatch DAC Gain Drift DAC Offset Voltage External Load Impedance Mute Attenuation (Vrms input) MIN 20 20 20 19,200 28,800 -85 10 90 TYP 1.0 1.0 1.0 104 100 90 -40 -40 -100 1.5 40 18 15 0.45 x AVdd 100 10 96 MAX 20,000 20,000 20,000 28,800 1 1 -85 0.5 0.5 50 UNITS Vrms Vrms Vrms Hz dB dB dB Hz Hz Hz Hz degree dB dB ms dB dB dB dB K K pF V dB dB ppm/C mV K dB Note: 1. 2. 3. 4. 5. 6. 7. 1 dB limits. If the sample rate is greater than or equal to 96 kHz the max frequency response becomes 40 kHz. The ratio of the rms output level with 1 kHz full scale input to the rms output level with all zeros into the digital input. Measured "A weighted" over a 20 Hz to a 20 kHz bandwidth. (AES17-1991 Idle Channel Noise or EIAJ CP-307 Signal-to-noise Ratio). 0 dB gain, 20 kHz BW, 48 kHz Sample Frequency 0.25 dB limits. The D/A freq. response becomes 40 kHz with sampling rates > 96 kHz. At 3dB the response range is from 20-22,500Hz at 48kHz, or 20-20,000Hz @ 44.1kHz or 20-45,000Hz @ 96kHz. Transition band is 40-60% of sample rate. Stop band begins at 60% of sample rate. Digital De-Emphasis OFF. The integrated Out-of-Band noise generated by the DAC process, during normal PCM audio playback, over a bandwidth 28.8 to 100 kHz, with respect to a 1 Vrms DAC output. 2-9460-D1-1-0-0801 7 PRELIMINARY INFORMATION 8/24/01 STAC9460/62 Two and Six-Channel, 24-Bit, 192 kHz Audio Codec 4. TYPICAL CONNECTION DIAGRAM 2 ohm * Ferrite Bead * * Suggested 5V 5% 0.1uF 1uF 21 DVdd 0.1uF 10uF 9 AVdd MCLK 14 20 11 12 10 15 16 17 13 18 19 RESET DIFF_L SCLK SDATA CS SDI1 SDI2 SDI3 SDATA_OUT D-SCLK D_LRCLK DAC_RF DAC_LR 28 27 26 25 24 23 DIFF_GND DIFF_R MIC_L MIC_R 3 4 5 1 2 STAC9460 Vref 6 0.1uF 10uF DAC_LF 7 10uF CAP DAC_RR DAC_CTR DAC_LFE DVss 22 AVss 8 0.1uF ** Terminate ground plane as close to power supply as possible Digital Gnd Analog Gnd Figure 2. Typical Connection Diagram 8 2-9460-D1-1-0-0801 PRELIMINARY INFORMATION 8/24/01 STAC9460/62 Two and Six-Channel, 24-Bit, 192 kHz Audio Codec 5. SERIAL INTERFACE Below is the figure for the serial interface between the STAC9460/62 and a C or P. All register settings and chip control are performed via this serial interface, except for the address LSB. Note: This functions as a standard 2-wire I2C compatible interface, however, the CS (chip select) line offers address flexibility and must be either hard wired to ground or tied to Vdd if no other chips are connected to the bus. Refer to Table 7.1.1 on page 14 for additional information. CS C / P S C LK SD AT A ST A C 9460 M C LK Figure 3. Serial interface to microcontroller or microprocessor 5.1. Clocking The STAC9460/62 derives its clock from an externally connected clock through the MCLK pin in combination with the Master CLocking Register, which is further explained in section 7.1.9. 5.2. Reset There are two types of resets as detailed below: * * A hard reset is achieved by driving the reset line low A soft reset is achieved by writing to the Reset/Status register (00h) By writing to the Reset/Status Register (00h) a reset for the Address Control Register will occur. Writing any value to this register performs a register reset, which causes all registers to revert to their default values. This soft reset will also place the I2C state machine in a "stop" condition, and will not continue to auto-increment through the address space. Additional information about the Address Control Register can be found in section 7.1.12. 2-9460-D1-1-0-0801 9 PRELIMINARY INFORMATION 8/24/01 STAC9460/62 Two and Six-Channel, 24-Bit, 192 kHz Audio Codec 6. DIGITAL AUDIO INTERFACE 6.1. I2S Serial Interface The STAC9460/62 communicates digital audio information through an I2S digital serial interface. The I2S interface can be configured with the standard I2S format, left justified, right justified or one line format. Input signals SDI1, SDI2, and SDI3 interface to the Left and Right Front Channels, Left and Right Rear Channels and the Center and LFE Channels respectively. The SDATA_OUT line outputs data from the two ADCs. I2S LINE SDI1 SDI2 SDI3 Alternate SDI1 SDATA_OUT ANALOG CHANNEL Left & Right Front Left & Right Rear Center & LFE All Channels Mic & Diff FUNCTION I2S data interface to DAC_LF & DAC_RF I2S data interface to DAC_LR & DAC_RR I2S data interface to DAC_CTR & DAC_LFE One line mode for all six channels I2S data interface from the ADCs Table 1. Digital Audio Interface Configuration ~ ~ ~ ~ D_LRCK D_SCLK SDIN 1/2/3 SDATA_OUT M S B Left Channel Right Channel ~ ~~ ~ ~ ~~ ~ ~ ~~ ~ -1 -2 -3 -4 -5 ~~ ~ ~ ~~ ~ ~ ~ ~~ ~ ~~ ~ ~~ ~ ~~ +5 +4 +3 +2 +1 L S B M S B -1 -2 -3 -4 -5 +5 +4 +3 +2 +1 L S B Figure 4. I2S Format ~ ~ ~ ~ Left Channel D_LRCK Right Channel ~ ~~ ~ ~~ ~ ~ ~~ ~ ~ ~~ ~ ~ ~~ ~ ~ ~ ~~ ~ ~~ D_SCLK SDIN 1/2/3 SDATA_OUT M S B ~~ ~ ~~ ~ -1 -2 -3 -4 -5 +5 +4 +3 +2 +1 L S B M S B -1 -2 -3 -4 -5 +5 +4 +3 +2 +1 L S B Figure 5. I2S Left Justified Format ~ ~ D_LRCK D_SCLK SDIN 1/2/3 SDATA_OUT Left Channel Right Channel ~ ~~ ~ ~~ ~ ~ ~ ~~~ ~~~ ~~~ 15 14 13 12 11 10 9 8 7 65 4 32 10 15 14 13 12 11 10 9 8 7 65 4 32 10 Figure 6. I2S Right Justified 16 Bit Format 10 2-9460-D1-1-0-0801 PRELIMINARY INFORMATION 8/24/01 STAC9460/62 Two and Six-Channel, 24-Bit, 192 kHz Audio Codec 6.2. LRCK SCLK SDIN 1/2/3 SDATA_OUT M S B Single Line Format ~ ~ ~ ~ ~ ~ ~ ~ Left Channel Right Channel ~ ~~ ~ ~ ~~ ~ ~ ~~ ~ Front ~~ ~ ~ ~~ ~ ~ ~ ~~ ~ ~ ~~ ~ ~ ~~ ~ ~ ~~ ~ ~ ~~ ~ ~~ ~~ ~ ~~ ~ ~~ ~ ~~ ~ ~~ ~ ~~ ~ -1 +1 L S B M S B -1 +1 L S B M S B -1 +1 L S B M S B -1 +1 L S B M S B -1 +1 L S B M S B -1 +1 L S B Rear Center Front Rear Bass Figure 7. Single Line 20 Bit Data Mode Timing Diagram Bits/Sample 20 SCLK Rate 128 Fs Notes 6 inputs, 2 outputs, BRM only Table 2. Single Line 20 Bit Data Mode, Data Valid on Rising Edge of SCLK The Single line data mode for the STAC9460 allows data all six channels to be input to the chip on a single SDATA_IN line, SD1 (Pin 15) and output to all six analog outs (Pins 2328). The ADC data will be valid during the first 20 SCLK cycles following a D_LRCLK transition. 6.3. I2C-Bus Interface The I2C-Bus of the STAC9460 operates in compliance with the I2C-Bus Interface Specification from Philips Semiconductor. The I2C-Bus for the STAC9460 does include an AutoIncrement feature not identified by the Phillips specification. For Example, a typical write would have the following format: START....Chip Address (8 bits)....Register Address(8 bits)....Data(Register Address 8 bits)....Data (Register Address +1 8 bits)....Data (Register Address +2 8 bits)....STOP. The addresses will increment through the end of the address space or until a "STOP" condition (as per I2C spec) is received by the part. For detailed information relating to the I2C, please reference the I2C-Bus Interface Specification from Philips Semiconductor. Additional information for the Address Registers can be found in section 7.1.12 Stop Start Repeated Start Stop ~ ~ ~ ~ SDA tbuf thdst thigh ~ ~ thdst tf tsusp ~ ~ ~ ~ SCL tlow thdd tsud tsust tr Figure 8. I2C Timing Diagram 2-9460-D1-1-0-0801 11 PRELIMINARY INFORMATION 8/24/01 STAC9460/62 Two and Six-Channel, 24-Bit, 192 kHz Audio Codec PARAMETER SYMBOL MIN MAX UNITS I C Mode (SDOUT < 47 k to ground) (Note 1) SCL Clock Frequency Buss Free Time Between Transmissions Start Condition Hold Time (prior to first clock pulse) Clock Low Time Clock High Time Setup Time for Repeated Start SDA Hold Time from SCL Falling (Note 2) SDA Setup Time to SCL Rising Rise Time of Both SDA and SCL Lines Fall Time of Both SDA and SCL Lines Setup Time for Stop Condition fscl tbuf thdst tlow thigh tsust thdd tsud tr tf tsusp 4700 4000 4700 4000 4700 300 250 100 100 1000 300 4700 KHz ns ns ns ns ns ns ns ns ns ns 2 Note: 1. 2. I2C is a registered trademark of Philips Semiconductor and requires a license for use. Data must be held for sufficient time to bridge the 300 ns transition time of SCL Table 3. I2C Mode Specifications 12 2-9460-D1-1-0-0801 PRELIMINARY INFORMATION 8/24/01 STAC9460/62 Two and Six-Channel, 24-Bit, 192 kHz Audio Codec 7. PROGRAMMABILITY REG # NAME Reset/Status Status Master Volume LF Volume RF Volume LR Volume RR Volume Center Volume LFE Volume Mic L Volume Mic R Volume De-Emphasis General Purpose Audio Port Control Master Clocking Powerdown Ctrl Powerdown Ctrl Revision Code Address Control Register Address Register 1. 2. D7 D6 D5 RESERVED D4 D3 D2 REF D1 DIFF RF MV 1 LF1 RF1 LR1 RR1 C1 B1 ML1 MR1 DEMRF D0 MIC LF MV0 LF0 RF0 LR0 RR0 C0 B0 ML0 MR0 DEMLF DEFAULT 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 00h 00h 80h 80h 80h 80h 80h 80h 80h 80h 80h 00h 00h AR MMute Mute LF Mute RF Mute LR Mute RR Mute C Mute LFE Mute ADCL Mute ADCR DEM1 MD MSS AL MV6 LF6 RF6 LR6 RR6 C6 B6 LFE MV5 LF5 RF5 LR5 RR5 C5 B5 RESERVED RESERVED CTR MV4 LF4 RF4 LR4 RR4 C4 B4 RR MV3 LF3 RF3 LR3 RR3 C3 B3 ML3 MR3 LR MV2 LF2 RF2 LR2 RR2 C2 B2 ML2 MR2 DEMLR RESERVED DEM0 HPFD DEM LFE RSVD DEM CTR HPFF ADF4 MCM2 ADF3 MCM1 ADC Bias PCTR 0 0 1 PRR 0 0 0 0 0 0 DEMRR RESERVED ADF2 MCM0 VREF PLR 0 0 1 ADF1 SRM1 DIG PRF 0 0 CS ADF0 SRM0 DIFF PLF 0 0 R/W RESERVED RESERVED RESERVED 00h 10h 00h 00h 00h 00h 56h ADR 0 0 0 ADL 0 0 1 PLFE Table 4. Programming Registers All registers not shown are reserved. Any bits marked "Reserved" should be written zero for normal operation 2-9460-D1-1-0-0801 13 PRELIMINARY INFORMATION 8/24/01 STAC9460/62 Two and Six-Channel, 24-Bit, 192 kHz Audio Codec 7.1. List of Registers 7.1.1. Reset/Status Register (00h) Writing any value to this register performs a register reset, which causes all registers to revert to their default values. Reading this register returns the corresponding status of the chip section represented by the bits. The bits are defined below: BIT D0 D1 D2 D3-D7 NAME MIC DIFF REF RESERVED DESCRIPTION Microphone inputs Differential inputs Reference RESERVED Table 5. Reset/Status Register 7.1.2. Status Register (01h) Reading this (read only) register returns the corresponding status of the chip section represented by the bits. The bits are defined below: BIT D0 D1 D2 D3 D4 D5 D6 D7 NAME LF RF LR RR CTR LFE AL AR DESCRIPTION Left front channel Right front channel Left rear channel Right rear channel Center channel Low Frequency Effects Channel Left ADC Right ADC Table 6. Status Register 7.1.3. Master Volume Register (02h) This register manages the output signal volume for all channels simultaneously and adds to the individual channel volume registers. The DAC range is from 0 to -96 dB with each step equivalent to approximately 0.75 dB. The MSB, bit D7, of the register is the mute bit for all DACs. When this bit is set, the output level is - dB. Bits MV6.. MV0 are used to control the master volume. MMUTE 0 0 1 MV6...MV0 000 0000 111 1111 xxx xxxx FUNCTION 0 dB Attenuation 96 dB Attenuation dB Attenuation Table 7. Master Volume Register 14 2-9460-D1-1-0-0801 PRELIMINARY INFORMATION 8/24/01 STAC9460/62 Two and Six-Channel, 24-Bit, 192 kHz Audio Codec 7.1.4. LF/RF, LR/RR, Center/LFE Output Channel Volume Registers(03h-08h) These registers determines the output signal volumes ranging from 0 dB to -96 dB with 0.75 dB steps. The MSB of the register is the mute bit for the channel. When this bit is set to 1, the outputlevel for that channel is - dB. Please note the STAC9462 only uses registers 3 and 4 for the Left and Right Front Channels. D7 0 0 1 D6...D0 000 0000 111 1111 XXX XXXX FUNCTION 0 dB Attenuation 96 dB Attenuation dB Attenuation Table 8. DAC Digital Volume Registers 7.1.5. Microphone Input Volume Registers (09h-0Ah) These registers control the gain/attenuation for each of the microphone inputs ranging from 0 dB to 10.5 dB, with each step corresponding to approximately 1.5dB. MSB 0 0 1 ML3...ML0 0000 1111 XXXX FUNCTION 0 dB 22.5 dB dB Attenuation MSB 0 0 1 MR3...MR0 0000 1111 XXXX FUNCTION 0 dB 22.5 dB dB Attenuation Table 9. Left and Right Mic Input Volume Registers 7.1.6. De-Emphasis Register (0Ch) This register is used to turn de-emphasis on and off for each channel. De-emphasis control bits D5..D0 (DEMLFE .. DEMLF) select whether or not de-emphasis is turned on or off for the given DAC and bits D7-D6 (DEM1 and DEM0) determine which response curve to use. BIT D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION De-emphasis OFF De-emphasis ON De-emphasis select for the LFE De-emphasis select for the CENTER De-emphasis select fot the RIGHT REAR De-emphasis select for the LEFT REAR De-emphasis select for the RIGHT FRONT De-emphasis select for the LEFT FRONT Table 10. On/Off De-emphasis Selection for Each Channel D7 .. D6 00 01 10 11 FUNCTION 32 kHz Response Curve 44.1 kHz Response Curve 48 kHz Response Curve 96 kHz Response Curve Table 11. De-emphasis Filter Selection 2-9460-D1-1-0-0801 15 PRELIMINARY INFORMATION 8/24/01 STAC9460/62 Two and Six-Channel, 24-Bit, 192 kHz Audio Codec 7.1.7. General Purpose Register (0Dh) The MSB (MD) selects between the MIC inputs and the DIFF inputs being routed to the ADCs. Bit D6 (HPFD) disables the ADC pass filter capability. The ADC High Pass FIlter Freeze, bit D4, maintains the high pass filter output's current DC offset HPFF 0 1 FUNCTION ADC High Pass Filter Not-Frozen ADC High Pass Filter Frozen Table 12. Bit D4: HPFD MD 0 1 FUNCTION Differential Input Selected Microphone Selected Table 13. Bit D5 Microphone Differential Mux By-Pass Control HPFD 0 1 FUNCTION ADC High Pass Filter Enabled ADC High Pass Filter Disabled Table 14. Bit D6 ADC High Pass Filter Disable 7.1.8. Audio Port Control (0Eh) The I2S port is controlled via the bits contained in this register. Formatting is controlled by the Audio Data Format bits, ADF4..ADF0 (bits D4 .. D0) of the register. The audio formats available are standard I2S, Left Justified, Right Justified (16, 20, or 24-Bit) and One Line. ADF4 .. ADF0 D4..D0 00000 00001 00010 01010 10010 00011 * AUDIO DATA FORMAT I2S Left Justified 16 bit Right Justified 20 bit Right Justified 24 bit Right Justified One Line All settings not shown are Reserved Table 15. Audio Data Format Selection 16 2-9460-D1-1-0-0801 PRELIMINARY INFORMATION 8/24/01 STAC9460/62 Two and Six-Channel, 24-Bit, 192 kHz Audio Codec 7.1.9. Master Clocking Register (0Fh) The Master Clocking Register is used to set the sampling rate of the converters to one of the three sample rate modes. Base rate, mid rate and high rate are selected with bits D1-D0 of the register. The master clock mode is set by selecting bits D4,,D2. The master clock mode is used generate an internal clock of the correct frequency based on the MCLK supplied by the user. For example, in the default mode (MCM=100 and SRM=00), MCLK in 512x, so if the sample rate is 48kHz then MCLK must be at 24.576MHz, which is 512x48kHz. Or with MCM=011 and SRM=01 (Mid Rate Mode) and a sample rate of 96kHz, then MCLK must be at 192x96kHz which is 18.432MHz. THe Master CLocking Register should be set before unmuting any DAC or ADC channels in register 02h to 0Ah. MCM2 (D4) set is default mode. SRM1SRM0 D1,D0 00 (default) 01 10 11 SAMPLE RATE SR 48 kHz 48 kHz < SR 96 kHz 96 kHz < SR 192kHz Reserved FUNCTION Base Rate Mode Mid Rate Mode High Rate Mode* Reserved Note:*ADC operates in Mid Rate Mode when High Rate Mode is selected, and will send each sample for two successive I2S frames. Table 16. Sample Rate Mode MCM2 .. MCM0 D4,D3,D2 MCLK Mode* BRM MRM HRM 000 128x 64x 32x 001 Reserved Reserved Reserved 010 256x 128x 64x 011 384x 192x 96x 100 (default) 512x 256x 128x 101 768x 384x 192x 110 Reserved Reserved Reserved 111 Reserved Reserved Reserved *Note: MCLK rate is relative to sample rate. (MCM * SR = MCLK). The number of D_SCLKs/D_LRCLK is independant of the MCLK mode for the STAC9460/62, but most controllers will generate D_SCLK at 1/2, 1/4, 1/8, or 1/16 the MCLK rate. Table 17. MCLK Mode 2-9460-D1-1-0-0801 17 PRELIMINARY INFORMATION 8/24/01 STAC9460/62 Two and Six-Channel, 24-Bit, 192 kHz Audio Codec 7.1.10. Powerdown Control Registers (10h-11h) The STAC9460 is capable of operating at reduced power when no activity is required. The state of power down is controlled by the Powerdown register. There are 11 separate power down commands. The Powerdown options are listed in Table 21. The bits can be used individually or in combination with each other, and control power distribution to the ADC's and DAC's. If the VREF option is selected it powers down the entire chip. Please note the rear, center, ad bass DAC's should be powered down for operation with the STAC9462. REG 11H BIT D0: PLF D1: PRF D2: PLR D3: PRR D4: PCTR D5: PLFE D6: ADL D7: ADR FUNCTION DAC_LF DAC_RF DAC_LR DAC_RR DAC_CTR DAC_LFE ADC Left ADC Right BIT D0: DIFF D1: DIG D2: VREF D3: ADC Bias D4: D5: D6: D7: REG 10H FUNCTION Differential Powers down I2S and De-emphasis Voltage Reference Powerdown ADC Bias circuitry X X X X * Note: Powers down I2S and De-emphasis X: denotes reserved Table 18. Powerdown Control 7.1.11. Revision Code Register (12h) The device Revision register contains a software readable revision-specific code used to identify performance, architectural, or software differences between various device revisions. 7.1.12. Address Control Register/Address Register (13h-14h) The address for the chip is defaulted to 55/56 or 54/55 for read and write. The LSB (bit D1) is programmable with the CS, pin 10. The Address Register (14h) can be changed. To change the address, AB must first be written to The Address Control Register (13h). A soft or hard reset will reset the Address Register to its default value with CS representing the LSB (D1). . 18 2-9460-D1-1-0-0801 PRELIMINARY INFORMATION 8/24/01 STAC9460/62 Two and Six-Channel, 24-Bit, 192 kHz Audio Codec 8. PIN DESCRIPTION 8.1. STAC9460 Pin and Signal Description STAC9460 MIC_L MIC_R DIFF_L DIFF_GND DIFF_R VREF CAP AVss AVdd CS# SCLK SDATA SDATA_OUT MCLK # denotes active low Figure 9. STAC9460 Pin Designation STAC9460 DAC_LF DAC_RF DAC_LR DAC_RR DAC_CTR DAC_LFE DVss DVdd RESET# D_LRCLK D_SCLK SDI3 SDI2 SDI1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 STAC9460 28-Pin SSOP 28 27 26 25 24 23 22 21 20 19 18 17 16 15 8.2. STAC9462 Pin and Signal Description STAC9462 MIC_L MIC_R DIFF_L DIFF_GND DIFF_R VREF CAP AVss AVdd CS# SCLK SDATA SDATA_OUT MCLK # denotes active low Figure 10. STAC9462 Pin Designation STAC9462 DAC_LF DAC_RF N.C. N.C. N.C. N.C. DVss DVdd RESET# D_LRCLK D_SCLK N.C. N.C. SDI1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 STAC9462 28-Pin SSOP 28 27 26 25 24 23 22 21 20 19 18 17 16 15 2-9460-D1-1-0-0801 19 PRELIMINARY INFORMATION 8/24/01 STAC9460/62 Two and Six-Channel, 24-Bit, 192 kHz Audio Codec 8.3. Digital I/O These signals connect the STAC9460/62 to an external C/P, DSP, and an external crystal. SIGNAL NAME TYPE DESCRIPTION RESET # I Master Hareware Reset MCLK I See Table 17 on page 17 for details CS# I Chip select SCLK I Serial data clock SDATA I/O Serial data input/output SDI1 I I2S digital data input for LF and RF channels SDI2 I I2S digital data input for LR and RR channels (STAC9460 only) SDI3 I I2S digital data input for Center and LFEchannels (STAC9460 only) SDATA_OUT O I2S Serial data output for ADC outputs D_LRCLK I I2S digital data left/right clock D_SCLK I I2S digital data bit clock # denotes active low Table 19. Digital Signal List 8.4. Analog I/O These signals connect the STAC9460/62 to analog sources and sinks, including microphones and seakers. SIGNAL NAME MIC_L MIC_R DIFF_L DIFF_GND DIFF_R DAC_LF DAC_RF DAC_LR DAC_RR DAC_CTR DAC_LFE TYPE I I I I I O O O O O O DESCRIPTION Left microphone input Right microphone input Left differential input Differential input common ground Right differential input Left front channel (LF) Right front channel (RF) Left rear channel (LR) (STAC9460 only) Right rear channel (RR) (STAC9460 only) Center channel (CTR) (STAC9460 only) Low Frequency Effects output (LFE) (STAC9460 only) Table 20. Analog Signal List 8.5. Filter/References . SIGNAL NAME VREF CAP TYPE O O DESCRIPTION Reference Voltage ADC reference Cap Table 21. Filtering and Voltage References 20 2-9460-D1-1-0-0801 PRELIMINARY INFORMATION 8/24/01 STAC9460/62 Two and Six-Channel, 24-Bit, 192 kHz Audio Codec 8.6. Power and Ground Signals SIGNAL NAME AVdd AVss DVdd DVss TYPE I I I I DESCRIPTION Analog Vdd = 5.0 V Analog Gnd Digital Vdd = 5.0 V or 3.3 V Digital Gnd Table 22. Power Signal List 9. PACKAGE DRAWING 2-9460-D1-1-0-0801 21 |
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